It should be understood that the invention may be practiced with various alternative components without altering the principles of the invention. For purposes of clarity, detailed descriptions of functions, components, and systems familiar to those skilled in the applicable arts are not included.
In general, the invention provides power supply, conversion, and charger control capabilities useful in a variety of applications and systems. The present patent application is related to U. The related applications share at least one common inventor and have a common assignee. Said related application is hereby incorporated herein for all purposes by this reference. The low power circuits and systems in presently preferred embodiments also include capabilities for ensuring that the system has access to sufficient power to operate in standby mode for significant periods of time, preferably including the capability for replenishing energy stored for use in standby mode.
Referring primarily to FIG. Deployed between the power conversion circuit and the output , an enabling circuit is configured to sense one or more output parameter associated with the output , and is further configured for switching the power conversion circuit between an active state and an inactive standby state in response to the sensed output parameter.
In this example of a preferred embodiment, the enabling circuit includes a low power, preferably on the order of nano-amps nA , comparator for sensing the DC output voltage V OUT at the output node Those skilled in the arts will appreciate that the enabling circuit comparator , or other component, may alternatively be configured to sense other output parameters such as, for example, current, power, impedance, capacitance, magnetic field s , or to receive an external signal such as a wireless transmission or timing signal.
An alternative implementation, for example, may include a comparator configured for monitoring output current instead of output voltage. If sufficient output voltage is available and the output current is below a certain predetermined threshold, then the power conversion circuit is not needed for supplying output current, and is placed in its standby state.
When the output voltage drops below a certain predetermined threshold, or when the output current exceeds a certain threshold, the conversion circuitry is again operated in the active state to supply the output current. It is believed that for many applications, monitoring output current without monitoring the output voltage will be sufficient for control of the system The enabling circuit is preferably operated using power from an energy storage device provided for that purpose, such as a battery or capacitor, e.
Preferably, when a load is detected at the DC output by the enabling circuit , the power conversion circuit is activated for converting an AC signal received at the input into a DC signal at the output terminal connected to the detected load not shown. Preferably, the comparator is configured to detect, based on one or more selected parameter s reaching selected threshold s , whether operation of the power conversion circuitry in either an active state or inactive standby state is required.
Preferably, when no load is detected at the DC output , the power conversion circuit is placed in an inactive standby state.
While the power conversion circuit is in the standby state, the comparator is powered by power stored in the enabling circuit , in this example a charge stored on the capacitor C OUT. Since the comparator is preferably configured to operate with extremely low quiescent current, a relatively small sized capacitor C OUT provides significant operating time.
When the voltage on the capacitor C OUT drops below a predetermined threshold level, the power conversion circuitry is activated. During the operation of the power conversion circuit in this active state, the charge on the capacitor C OUT is replenished. When the sensed output parameter, in this example voltage V OUT , reaches a predetermined threshold the power conversion circuitry turns off, entering the inactive state, and only the low-power comparator remains on, minimizing the system power consumption.
In an alternative embodiment of the invention, an example of which is illustrated in FIG. The system , as illustrated in FIG. Using this configuration, the enabling circuit receives a signal from the load communicating that power is required to be supplied at the output Accordingly, the enabling circuit causes the conversion circuit to operate in the active mode. When a signal is received indicating that power is not required at the output , the enabling circuit causes the conversion circuit to enter the standby mode and stop consuming and supplying power.
The enabling circuit then continues to monitor the output for a signal which would again cause it to place the converter circuit in the active state. Now referring primarily to FIG. In this circuit , the presence of a load at the output is detected by the operation of a switch , preferably located in the adapter plug in typical power converter applications. When a load is present at the output , the converter circuit is enabled by operation of the enabling circuit When no load is detected at the output by operation of the switch , the power conversion circuitry is placed in its inactive standby state and the enabling circuit is placed in low power mode, drawing its power from an associated power storage device, in this example capacitor C CONTROL.
The load switch can be implemented in a variety of ways as long as communication with the enabling circuit is provided. In a preferred embodiment, a mechanical switch is used. In alternative implementations, a proximity switch, such as a capacitive, inductive, optical, magnetic, resistive, or infrared sensor activated switch may be used without departure from the invention.
Additional embodiments of the low power converter of the invention further address the challenge of guaranteeing system startup when the converter system has been idle for an extended period of time. In such a scenario, the power storage element of the enabling circuit, e.
An alternative embodiment of low power converter circuitry is shown in FIG. A timer is coupled to the primary side of the power conversion circuit In this configuration, the system may be configured to automatically turn on periodically and convert power in its active state for a brief period of time. Thus, the output capacitor C, or other suitable energy storage device, may be recharged from time to time, ensuring that the system retains sufficient power to continue monitoring the output for detection of demand for DC output requiring the operation of the power conversion circuit in its active mode.
As an alternative to the use of a timing signal, additional external signals may be used such as wired or wireless communications signals suitable for causing the conversion circuitry to recharge the enabling circuit power source, e.
As illustrated in the schematic diagram of FIG. As indicated by arrow , the AC signal on the primary side of the conversion circuit operates to pump charge across the capacitor C PUMP , providing a start-up voltage for the enabling circuit connected with the secondary side of the conversion circuit A Zener diode Z CLAMP coupled between the enabling circuit and ground is preferably used to limit the voltage sufficiently to protect the circuit from over voltage.
The size of the capacitor C PUMP may be selected to limit the power transmission to the secondary side of the conversion circuit , and thus also limit the total power dissipated by the enabling circuit in this configuration.
An additional implementation of a preferred embodiment of a low power converter system is illustrated in FIG. In this circuit implementation, startup on the primary side is guaranteed using an ultra-low power regulator This regulator is preferably constructed use minimum nano-amps or lower practicable bias current. This bias current is preferably be dynamic in nature, so that the regulator stability or other performance parameters adjust based on the regulator loading or other parameters.
Use of an ultra-low power regulator, e. This LDO can be implemented according to the principles of the invention using any of a large number of regulator topologies with either a FET or a bipolar output stage. An additional advantage of this ultra-low power architecture is that the regulator does not require high voltage tolerance.
The CONT pin may also be optionally provided with an additional decoupling capacitor to improve system stability. To further improve system efficiency after startup, the power for the primary side can be provided by an additional winding or additional taps on the transformer This provides an efficient power conversion from the high voltage input to the lower voltage required to power the primary side circuits.
In an additional variation of the circuit architecture introduced in FIG. An additional capacitor can be placed from CONT to GND to provide sufficient energy storage to facilitate startup, but is not required. After the initial startup of the system , power is supplied from the transformer to VCC. The invented ultra-low power converter architecture also facilitates the implementation of a number of additional improvements on the primary side The first is clock dithering to reduce emissions.
Using either digital control of the gate drive frequency or analog distortion of the gate drive signal, the transistor M 2 switching frequency can be varied continuously during operation. This limits the amount of energy emitted at any particular frequency of operation.
Further mitigation of emission may be realized with M 2 gate drive slew control. Emissions can be reduced by limiting or otherwise controlling the M 2 gate drive slew rate. This can be achieved using a driver with variable resistance, a driver with a dynamically adjustable or resistively limited supply, staged turn-on of multiple portions of the driver circuit, use of a single or multiple current sources to drive the gate, or use of an optional external resistor RD as shown in FIG.
The controller can also be used to limit the switching frequency of the FET M 2. This helps constrain the frequency of emitted energy and can prevent emission in the audio band, which may be particularly advantageous in some application contexts.
To further improve performance, i. In this technique, the timing of the gate driver signal is adjusted to minimize the magnitude and occurrence of current spikes in the system It has been determined that system cost can also be reduced by removing the L 2 winding from the system illustrated in FIG.
This is done however at the expense of increasing power dissipation in the primary side In embodiments with L 2 removed or omitted, the transistor M 1 acts as a shunt regulator, and needs to hold off the voltage between the rectified AC signal and the voltage required by IC 1. The control on the primary side can be done using all analog, all digital, or any other partitioning of analog and digital circuits.
Loop control can be achieved using any combination of voltage or current sensing on the primary side , or voltage or current sensing on the secondary side with the use of an isolated element, or other communication element. Change AC voltage to DC voltage and bring power to electronic devices while protecting them from harmful electromagnetic interference EMI.
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